→ Familiarize with various stages and interdependencies of Industry standard IP and SOC development flows at a high-level.
→ Understand the major steps involved in the generation of gate-netlist from RTL.
→ Thorough understanding of FSM coding styles through execution and analysis of hands-on exercises.
→ Get introduced to logic synthesis and leaf-cell libraries.
→ Understand how RTL gets mapped to gate-level implementation by means of schematic analysis.
IP and SOC development cycles - High level overview:
→ Various stages of IP Development cycle from Specification to IP packaging.
→ Various stages of SOC development cycle from Specification to Tape-out.
→ A typical SOC block-diagram showing IP blocks and interface buses
Overview of Gate-netlist generation:
→ The three major steps in the gate-netlist generation:
- Logic synthesis process
- Scan insertion in the gate-netlist
- Formal Verification (Equivalence checks)
LAB4 : Bring up the lab exercises and complete the analysis of the FSM design that is expected to be completed as part of the exercise.
LAB5 : Review the RTL codes for the shift register and the Mealy FSM implementation that are planned to be taken through the synthesis experiments.
LAB5 : Walk through the logic synthesis flows for the shift register code implementation and schematic review of the resultant gate-netlist.
LAB5 : Understand the concept of leaf-cell library used during synthesis, using the TSMC018 .lib example.
LAB5 : Discuss the synthesis experiment using the Mealy FSM Verilog code that is expected to be completed as part of LAB5 exercises.
Assignment: Execute LAB5 exercises